The present invention relates to a semiconductor device and a method of manufacturing the same, which is, for example, suitably applicable to a semiconductor device including a trench gate type IGBT (Insulated Gate Bipolar Transistor).
As to a power semiconductor device including an IGBT, it is desirable to have features of a low on-state voltage and a high-speed turn-off. A first method to achieve the low on-state voltage in the trench gate type IGBT is to provide a region where a pitch between trench gates is wide and a region where a pitch between trench gates is narrow. Further, in the region where the pitch between the trench gates is wide, a floating layer is provided in place of a contact to an emitter electrode (see, for example, Japanese Unexamined Patent Application Publication No. 2013-140885 [Patent Document 1]). In such a case, a hole current flows only in a portion where a spacing between the trench gates is narrow and a hole concentration increases near the emitter electrode. Since electrons are induced there (carrier injection effect), the on-state voltage can be decreased.
A second method for achieving the low on-state voltage is to narrow a pitch spacing while allowing the pitch between the trench gates to be uniform. According to the second method, in order to reduce the gate capacitance, emitter potential is given in place of gate potential to some of the trench gates (see, for example, Japanese Unexamined Patent Application Publication No. 2003-188382 [Patent Document 2]).
As a method similar to the second method described above, Non-patent Document 1 discloses a following method. In the method, the width of mesa between trenches is minimized by widening a width of the trench gate itself, which prevents an easy flow of the hole current. As a result, the carrier injection effect is enhanced.
Further, though not directly related to the above, in the trench gate type IGBT, in order to prevent an electric field concentration onto a bottom portion of the trench gate, there is a case where a floating P region is provided near the bottom portion of the trench gate (see, for example, Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2003-520430 [Patent Document 3]).    [Patent Document 1]    Japanese Unexamined Patent Application Publication No. 2013-140885    [Patent Document 2]    Japanese Unexamined Patent Application Publication No. 2003-188382    [Patent Document 3]    Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2003-520430    [Non-patent Document 1]
M. Sumitomo et al., “Low Loss IGBT with Partially Narrow Mesa Structure (PNM-IGBT)”, Proceedings of the 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12, pp. 17-20, and 2012.